中圖分類號： TN710 文獻標識碼： A DOI：10.16157/j.issn.0258-7998.211907 中文引用格式： 游月娟，劉德喜，劉亞威，等. DC-60 GHz硅基垂直互聯結構仿真設計[J].電子技術應用，2022，48(1)：142-145，151. 英文引用格式： You Yuejuan，Liu Dexi，Liu Yawei，et al. Design of DC-60 GHz silicon based vertical interconnection structure[J]. Application of Electronic Technique，2022，48(1)：142-145，151.
Design of DC-60 GHz silicon based vertical interconnection structure
You Yuejuan，Liu Dexi，Liu Yawei，Shi Lei
Beijing Institute of Telemetry Technology，Beijing 100094，China
Abstract： A vertical interconnection structure based on a stack of multi-layer silicon interposer boards is designed. The simulation results of the vertical interconnection structure of the two interlayer structure not considering and considering the SiO2 layer on the silicon surface were compared in the DC-60 GHz frequency band. The existence of the SiO2 layer has an impact on the radio frequency performance such as resonant frequency and impedance. The parameters of the latter vertical interconnection structure are optimized, its RF transmission performance is good, and the return loss S11 is less than -30 dB when the frequency is below 40 GHz, the overall S11 is less than -15 dB below 60 GHz, and the insertion loss S12 is greater than -0.32 dB below 50 GHz. This paper simulates and analyzes the influence of the thickness of SiO2 insulation layer on the silicon surface on the transmission performance of the radio frequency signal. The results show that appropriately increasing thickness of SiO2 insulation layer can help optimize the performance of the vertical interconnection structure.
Key words : 3D integration；stack of multi-layer silicon interposer；vertical interconnection structure；transmission performance